Semiconductor fabrication processes frequently involve formation of electrical interconnects within openings. The desired aspect ratio of the openings is increasing for various reasons, including, for example, to compensate for losses in capacitance or inductance. As the aspect ratio increases, it becomes increasingly difficult to conformally fill openings with traditional processes. FIGS. 1 and 2 illustrate an exemplary prior art process, and a problem that can occur during an attempt to form an electrical interconnection within an opening.
FIG. 1 shows a semiconductor construction 10 at a preliminary processing stage. Construction 10 comprises a base 12. The base can comprise, consist essentially of, or consist of monocrystalline silicon lightly-doped with background p-type dopant. The base 12 can be referred to as a “substrate”, and/or various combinations of structures can be referred to as a “substrate”. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A conductive block 14 is formed over base 12. Block 14 can correspond to, for example, a digit line.
An insulative material 16 is formed over base 12 and over block 14. Insulative material 16 can comprise, for example, borophosphosilicate glass (BPSG).
An opening 18 is etched through insulative material 16 to an upper surface of conductive block 14. Opening 18 can be formed utilizing, for example, photolithographic processing to generate a patterned photoresist mask (not shown) which defines a location for opening 18, followed by an etch into material 16 to generate the opening 18, and subsequent removal of the photoresist mask. The opening is shown having vertical sidewalls, but it is to be understood that such is an idealized structure. Frequently the opening will have non-vertical sidewalls due to limitations in etching processes.
Referring to FIG. 2, a first conductive material 20 is formed over insulative material 16 and within opening 18. Conductive material 20 can comprise, for example, a metal nitride (such as titanium nitride) and can be formed by, for example, chemical vapor deposition. A second conductive material 22 is formed over conductive material 20. Second conductive material 22 can comprise, for example, tungsten and can also be formed by, for example, chemical vapor deposition. The first layer 20 can function as an adhesive for adhering the second layer 22 to insulative material 16.
A problem that occurs during deposition of one or both of materials 20 and 22 is that the conductive material can grow non-conformally at upper corners proximate opening 18 to form extensions 24. The extensions 24 can ultimately pinch off the top of opening 18 before the opening has been conformally filled with conductive materials 20 and 22. Accordingly, a void 26 remains in the opening. Such void is frequently referred to as a “keyhole”. The shape of the opening 18 and keyhole 26 are shown diagrammatically in FIGS. 1 and 2, and it is to be understood that the opening and keyhole can have other shapes. Such other shapes can include a concave “bow” near the top of opening 26 due to limitations in the ability of etches to form the shown vertical sidewalls. The bow can provide additional complications to a conformal fill which can exacerbate keyhole problems and lead to formation of large keyholes just below the upper surface of material 16. Such large keyholes can undesirably be exposed in subsequent polishing processes. It is desired to develop new methods for filling openings which alleviate, and preferably prevent, formation of keyholes.